Echelon I/O Model Reference for Smart Transceivers and Neu Uživatelský manuál Strana 120
- Strana / 209
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
110 Serial I/O Models
Table 42. SPI Slave Mode for Series 5000 Devices
Parameter
Value for
80 MHz
Value for
40 MHz
Value for
20 MHz
Value for
10 MHz
Value for
5 MHz
Max burst rate 10 Mbps 5 Mbps 2.5 Mbps 1.25 Mbps 625 kbps
Max burst size 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes
Min burst spacing
(from start of one
burst to next)
100 μs 200 μs 400 μs 800 μs 1600 μs
Max sustained data
rate
430 kbps 210 kbps 100 kbps 40 kbps 25 kbps
Sustained reception in slave mode at high bit rates can starve the application
processor and cause overruns, and presents a possible risk of watchdog timeout.
Care must be given to allow the Smart Transceiver to process received bytes in a
timely manner. Master mode has no such restriction because the Smart
Transceiver regulates the data transfer.
The clockedge and invert keywords are used to determine the point at which data
is sampled and the idle level of the clock signal. By default, the clock signal is
idle at the logic 1 level. Use the invert keyword to change the idle state to
correspond to a logic 0 level. Common SPI implementations use the terms clock
phase (CPHA) and clock polarity (CPOL) to determine the behavior of the clock
signal during SPI transmissions. These terms relate directly to the clockedge
and invert keywords used in the I/O object declaration, as described in
Table 43.
Table 43. Relating CPHA and CPOL to Neuron C Declarations
SPI Clock Signal State Neuron C Declaration
CPHA
0
1
clockedge(-)
clockedge(+)
CPOL
0
1
invert
[default]
The active edge of the clock is determined by the clockedge and invert keywords.
If the clock signal is idle at logic 1 (default), then clockedge(-) indicates that the
falling edge of the clock signal is active. If the invert keyword is used, the rising
edge of the clock signal would be active (see
Figure 39 and Figure 40 on page
111). In-phase interfaces (CPHA=1) present the data bit on the first transition of
the clock signal, and latch it on the second transition. Out-of-phase interfaces
(CPHA=0) present the data bit before the first transition of the clock signal, and
latch it on the first transition.
- I/O Model Reference for Smart 1
- Transceivers and Neuron Chips 1
- Welcome 3
- Audience 3
- Related Documentation 3
- Mini FX User’s Guide 4
- Series 5000 Chip Data Book 4
- Table of Contents 5
- Introduction 11
- Overview 12
- Direct I/O Models 14
- Parallel I/O Models 14
- Serial I/O Models 15
- Overlaying I/O Objects 18
- I/O Timing Issues 22
- Information 24
- Multiplexing I/O Models 28
- General I/O Functions 28
- Neuron C Reference Guide 29
- I/O Events 31
- Neuron C Programmer’s Guide 31
- Using Functions or Events 35
- Timer/Counter I/O Models 38
- Output Models 39
- Bit Input/Output 42
- Bit Input Example 45
- Bit Output Example 45
- Byte Input/Output 45
- Byte Input Example 47
- Byte Output Example 48
- Leveldetect Input 48
- Nibble Input/Output 50
- Nibble Input Example 53
- Nibble Output Example 53
- Touch Input/Output 53
- Muxbus Input/Output 62
- Parallel Input/Output 65
- Master Program 71
- Slave Program 72
- Slave B Mode 73
- Token Passing 76
- Handshaking 76
- Transferring Data 76
- Resynchronization Procedure 77
- Using the IRQ Signal 80
- Bitshift Input/Output 86
- Bitshift Input Example 90
- Bitshift Output Example 90
- I2C Input/Output 90
- Magcard Bitstream Input 94
- Magcard Input 96
- Magtrack1 Input 99
- Programming Considerations 100
- Syntax 101
- Example 102
- Neurowire Input/Output 102
- Hardware Considerations 102
- Neurowire Master Mode 103
- Neurowire Slave Mode 104
- SCI (UART) Input/Output 108
- Serial Input/Output 113
- Serial Input Example 117
- Serial Output Example 117
- SPI Input/Output 117
- SPI Master 122
- SPI Master (Neurowire 122
- SPI Slave 123
- Wiegand Input 128
- Timer/Counter Input Models 133
- Dualslope Input 135
- Neuron C Resources 138
- Edgelog Input 139
- Infrared Input 144
- Ontime Input 148
- Period Input 151
- Pulsecount Input 155
- Quadrature Input 158
- Totalcount Input 161
- Timer/Counter Output Models 165
- Edgedivide Output 166
- Frequency Output 169
- Infrared Pattern Output 172
- Oneshot Output 175
- Pulsecount Output 178
- Pulsewidth Output 181
- Stretched Triac Output 184
- Triac Output 189
- Example 1 192
- Example 2 193
- Triggered Count Output 193
- Timer/Counter Periods and 197
- Resolution 197
- InputClock 199
- And so on 200
- Period = 201
- Frequency = 1 / 201
- 196 Index 206
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